Principal SRAM Design Engineer

Design
India
May 9, 2025
Full Time

Job Description

Broadcom is seeking a Principal SRAM Design Engineer to sign up for our main-aspect Memory IP crew. This function gives the opportunity to architect and supply nation-of‑the‑art SRAM blocks for slicing‑area ASICs and SoCs deployed throughout networking, storage, broadband, and wi-fi markets.

Key Responsibilities

Architect and Design

  • Define microarchitecture of high‑density, low‑power, excessive‑pace SRAM macros
  • Evaluate trade‑offs amongst overall performance, location, and strength to satisfy machine‑stage necessities

Physical Implementation Collaboration

  • Partner with format and verification teams to ensure DRC‑ and LVS‑compliant designs
  • Guide floorplanning and cell placement optimization for timing closure

Verification & Characterization

  • Develop and execute RTL and gate‑degree simulations to validate functional correctness
  • Perform silicon characterization and debug to pleasant‑tune timing corners and voltage thresholds

Process & Technology Scaling

  • Lead porting of SRAM IP to superior process nodes (e.G., 7nm, 5nm, beneath)
  • Collaborate with foundry partners to combine procedure‑precise upgrades

Mentorship & Leadership

  • Mentor junior engineers on reminiscence layout satisfactory practices and DFT methodologies
  • Drive design opinions and provide technical guidance across cross‑purposeful groups

Required Qualifications

Educational Background

  • Master’s or Ph.D. In Electrical Engineering, Microelectronics, or related field

Experience

  • 10+ years designing SRAM for digital ASICs, with at the least five years at advanced nodes (≤7nm)
  • Proven track record of handing over excessive‑performance memory IP that meet stringent PPA targets

Technical Skills

  • Proficient in Verilog/SystemVerilog for RTL layout and UVM for verification
  • Deep expertise of transistor‑degree behavior, compact modeling, and timing evaluation
  • Hands‑on experience with reminiscence compiler equipment (e.G., Synopsys, Cadence, Mentor)

Soft Skills

  • Strong analytical and problem‑solving abilities
  • Excellent written and verbal verbal exchange for technical documentation and presentations
  • Demonstrated management in a matrixed, collaborative surroundings
  • Preferred Qualifications
    Experience with low‑voltage SRAM layout and reliability (e.G., soft‑mistakes charge evaluation)
  • Background in embedded reminiscence security features (e.G., physical unclonable functions)
  • Familiarity with enterprise requirements for reminiscence BIST and diagnostic applications

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